Verilog HDL design examples / (Record no. 58126)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 02641cam a2200397Ii 4500 |
| 001 - CONTROL NUMBER | |
| control field | 9781315103846 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 180706t20172018flu b ob 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781315103846 |
| Qualifying information | (e-book : PDF) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781351596282 |
| Qualifying information | (e-book: Mobi) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9781138099951 |
| Qualifying information | (hardback) |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1201/b22315 |
| Source of number or code | doi |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)1006879226 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | FlBoTFG |
| Transcribing agency | FlBoTFG |
| Description conventions | rda |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7868.D5 |
| Item number | C3948 2017 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | COM |
| Subject category code subdivision | 059000 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC |
| Subject category code subdivision | 008010 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC |
| Subject category code subdivision | 009070 |
| Source | bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.381 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Cavanagh, Joseph, |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Verilog HDL design examples / |
| Statement of responsibility, etc. | by Joseph Cavanagh. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | First edition. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Boca Raton, FL : |
| Name of producer, publisher, distributor, manufacturer | CRC Press, |
| Date of production, publication, distribution, manufacture, or copyright notice | [2017]. |
| 264 #4 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Date of production, publication, distribution, manufacture, or copyright notice | ©2018 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 online resource (673 pages) |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Source | rdacarrier |
| 505 00 - FORMATTED CONTENTS NOTE | |
| Title | chapter 1 Introduction to Logic Design Using Verilog HDL / |
| Statement of responsibility | Joseph Cavanagh -- |
| Title | chapter 2 Combinational Logic Design Using Verilog HDL / |
| Statement of responsibility | Joseph Cavanagh -- |
| Title | chapter 3 Sequential Logic Design Using Verilog HDL / |
| Statement of responsibility | Joseph Cavanagh -- |
| Title | chapter 4 Computer Arithmetic Design Using Verilog HDL / |
| Statement of responsibility | Joseph Cavanagh. |
| 520 3# - SUMMARY, ETC. | |
| Summary, etc. | The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles—including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs) |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Digital electronics |
| General subdivision | Computer-aided design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Verilog (Computer hardware description language). |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | CRC Press. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| International Standard Book Number | 9781138099951 |
| Record control number | (DLC) 2017022734 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://www.taylorfrancis.com/books/9781315103846">https://www.taylorfrancis.com/books/9781315103846</a> |
| Public note | Click here to view. |
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